An Optimized Implementation of 64-bit Carry Select Adder in Fpga Technology

V.BHARATHI 1 D.Y. PUSHPA MITRA 2 honey.bharathi76 @gmail.com [email protected] 2 PG Scholar,Dept of ECE, Sreenivasa Institute of Technology and Management Studies (Autonomous) Murkambattu, Chittoor, JNTU Anatapur University Associate Professor,Dept of ECE, Sreenivasa Institute of Technology and Management Studies (Autonomous) Murkambattu, Chittoor JNTU Anatapur University . Abstract: In several data-processing processors Carry Select Adder (CSLA) is one quickest adders used to perform arithmetic functions. The approaching technologies depicts that there is a scope for reducing the space and power consumption in the CSLA. This work uses a straightforward gate level modification to considerably cut back the space and power of the CSLA. Based mostly on this modification CSLA designs have been developed and will be compared with the regular CSLA design. The projected style has reduced space and power as compared with the regular CSLA with solely a slight increase in the delay. This work evaluates the performance of the projected styles in terms of delay, area, power, and their product by hand with logical effort and through custom style and layout inzero.18-m CMOS method technology. The results analysis shows that the projected CSLA structure is healthier than the regular CSLA.